1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, it relates to a semiconductor device in which a MOS transistor is formed on an SOI substrate or a multilayer SOI substrate, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, the density of integration of a large-scale integrated circuit has been heightening rapidly. Consequently, the gate lengths of MOS transistors mounted in MOS type integrated circuits have become 0.2 μm or less at the level of practical use and have reached 0.05 μm at the level of researches. In order to realize a high performance and a long-term reliability in such micro MOS transistors, the structure of a MOS transistor must be optimized considering various factors.
In order to realize a still higher density of integration in a MOS type integrated circuit, the size of the whole MOS transistor must be made still smaller. Moreover, even when the size of the MOS transistor is made smaller, the gate length thereof needs to be shortened lest such a basic performance as current driving capability should degrade.
However, when the gate length is shortened, a phenomenon called “short channel effect” occurs conspicuously. Here, the “short channel effect” is the phenomenon that, as the gate length decreases, the threshold voltage and source/drain withstand voltage of the transistor lower and a subthreshold coefficient increases.
A method wherein the impurity concentration of a channel portion is increased with decrease in the gate length, is usually employed with the intention of suppressing such a short channel effect to incarnate a transistor of good characteristics.
However, when a micro MOS transistor is fabricated on the basis of such general principles, the capacitance of a pn junction formed between the drain of the MOS transistor and the substrate of the MOS type integrated circuit increases, and hence, a time period expended on the charge/discharge of a parasitic capacitance increases to lower the speed of a circuit operation.
Hitherto, micrifying transistors (optimizing the structures thereof) has been done while these difficult problems have been solved in well-balanced fashion. It is very difficult, however, to further micrify transistors and to heighten the density of integration of an integrated circuit by solving the problems of manufactural technology such as microfabrication techniques, design technology for an integrated circuit system as well as a complicated circuit, and so forth.
Meanwhile, a method wherein transistors are formed on an SOI substrate has been proposed.
In general, the transistors fabricated on the SOI substrate are structurally classified into the two types of “complete depletion type” and “partial depletion type”. When the concentration of an impurity to be introduced into the silicon layer of a channel portion in NMOS/SOI or PMOS/SOI and the thickness of this silicon layer have been determined, the relationship in magnitude between the maximum value of the width of a depletion layer (the maximum depletion-layer width), which is predominated by the impurity concentration and the thickness of the silicon layer of the channel portion is determined. That is, the transistor in which the maximum depletion-layer width is larger than the thickness of the silicon layer of the channel portion is called “complete depletion type SOI transistor”, while the transistor in which the maximum depletion-layer width is smaller than the thickness of the silicon layer of the channel portion is called “partial depletion type SOI transistor”.
However, in a case where an integrated circuit employing the SOI substrate is operated with a very low voltage of, for example, 1 V or below, it involves the problem that a leakage current in a standby mode enlarges and that a consumption current increases in the standby mode.
In this regard, body contact SOI of four terminals has been proposed in order to solve the problem (for example, Japanese Patent Application Laid-open No. 10(1998)-141487).
As shown in FIG. 10 of the accompanying drawings, the body contact SOI is intended to dynamically change threshold voltages in such a way that a P-type well 82 and an N-type well 83, which are formed in the semiconductor layer 81 of an SOI substrate 80, are fully isolated by an element isolation region 84, and that the P-type well 82 and N-type well 83 are respectively controlled by bias voltages applied to well contacts 85 and 86.
With this method, however, the contact for affording an electric potential needs to be led out directly from the P-type well 82 of the semiconductor layer 81, and inevitably the semiconductor layer 81 needs to be thickened, so that a channel region becomes partially depleted. Moreover, since the contacts are led out directly from the wells of low impurity concentrations, well resistances are influential in relation to the distances between contact portions and transistors, and a substrate voltage is not uniformly applied, resulting in the problem that the threshold voltages become discrepant in the respective transistors contrariwise.
Proposed as another method is one wherein, as shown in FIG. 11, high-concentration impurity layers are formed in parts of the surface of a P-type silicon substrate which is a support substrate. More specifically, this method constructs a CMOS circuit wherein a high-concentration P-type region 89 is arranged in the vicinity of that interface between the support substrate 88 and a buried oxide film 87 which corresponds to the channel of an NMOS transistor, while an N-well 90 is arranged in the surface part of the support substrate 88 underlying a PMOS transistor, and a high-concentration N-type region 91 is disposed in the vicinity of that interface between the support substrate 88 and the buried oxide film 87 which corresponds to the channel of the PMOS transistor (refer to Japanese Patent Application Laid-open No. 8(1996)-32040, and Proceeding 1995 IEEE International SOI Conference 14p, October 1995).
In this semiconductor device, a depletion layer on the side of the support substrate 88 as is formed by the rise of a drain voltage can be restrained from spreading up to the lower parts of channel regions. Therefore, the parameters, such as threshold voltages and mobilities in channel, of the complete depletion type SOI transistors are stabilized, and the operating speed of the circuit can be raised.
In the semiconductor device, however, merely the N-well 90 is fixed at a supply voltage, and the threshold voltage of the transistor is not controlled by positively changing the voltage of the well. It is accordingly difficult to lower a leakage in a standby mode and a consequent consumption current in the standby mode.
Further, a semiconductor device wherein, as shown in each of FIGS. 12(a) to 12(d), a plus voltage or/and a minus voltage is/are directly applied to the back surface of a support substrate 92, thereby to control threshold voltages, has been proposed in Japanese Patent Application Laid-open No. 10(1998)-125925.
Since, however, an applied voltage to a well 93a or 93b is limited within the range of the reverse withstand voltage of a pn junction in the support substrate 92, the semiconductor device has the problem that the applied voltage is little versatile. Besides, a contact must be led out onto the side of a front-surface semiconductor layer in order to apply the voltage to the well, and this remains as a problem from the viewpoint of micrifying the semiconductor device. Further, it is not practical that, as shown in each of FIGS. 12(c) and 12(d), both the plus and minus voltages are applied directly to the support substrate 92 without forming any well. Moreover, the semiconductor device in each of FIGS. 12(a) to 12(d) consists in that a higher operating speed is attained by lowering the parasitic capacitance of SOI transistors, and that a body voltage is controlled so as to accumulate large numbers of carriers in the regions of the front-surface silicon layer underlying the body, thereby to control the threshold voltages and to suppress a floating body effect. That is, the semiconductor device is not intended to change a bias voltage between in the operating state and the standby state of a semiconductor circuit.
Also proposed is a structure wherein, as shown in FIG. 13, a threshold voltage is set low by employing a dual SOI structure which consists of a first insulating layer 94, a first semiconductor layer 95, a second insulating layer 96 and a second semiconductor layer 97 (refer to Japanese Patent Application Laid-open No. 8(1996)-222705).
In this semiconductor device, however, the back surface of the substrate is covered with an insulating film, no means is provided for controlling the threshold voltage, and merely a substrate bias effect is relieved to stabilize the threshold voltage. It is impossible to lower the leakage current of a transistor in the standby mode thereof and consequently the consumption current of the transistor in the standby mode thereof.
As thus far explained, even in the conventional semiconductor integrated circuit employing the SOI transistors, the parasitic capacitance have existed between the source/drain regions and the lower parts of the channel regions, and they have formed the cause for hindering the attainment of a higher operating speed. Besides, in the conventional SOI transistors, there has been known the method of controlling the threshold voltages and suppressing the floating body effect by controlling the body potential, but the method has had the problem that a satisfactory effect is not attained because of the various causes.